Reducing Delay Uncertainty in Deeply Scaled Integrated Circuits Using Interdependent Timing Constraints

Interdependent setup-hold times are exploited during the design process to reduce delay uncertainty. Considering this interdependence only during static timing analysis (STA) is insufficient to fully exploit the capabilities offered by interdependence. This result is due to the strong dependence of STA on the specific circuit, cell library, and operating frequency. Interdependence is evaluated in this paper for several technologies to determine the overall reduction in delay uncertainty rather than improvements in STA. The increasing efficacy of interdependence in deeply scaled technologies is also demonstrated by investigating the effect of technology scaling on interdependent timing constraints.