Fault Models and Tests for a Prototype 4-level DRAM
نویسنده
چکیده
This Diplomarbeit describes the development of a fault model and appropriate tests for a 4-level dynamic random-access memory (DRAM). The considered DRAM stores two bits in one cell using four signal voltage levels and three reference voltages. These voltage levels are created by charge sharing schemes which lead to sequential sensing and restore operations. Both operations are more complicated than in conventional 2-level DRAMs and result in new faulty behaviors for several defects. Starting with a list of physical defects that are expected to be the most likely to occur, a new fault model for the 4-level DRAM is developed by using both manual circuit analysis and analog circuit simulation. For this fault model a new 8n/4m test (n = number of cells, m = number of bits) is proposed that detects all functional faults of the fault model. Finally, some alternative test strategies for testing the 4-level DRAM are brie y described.
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