Efficient Explicit Pulsed Double Edge Triggered Flip-Flop by Using Dependency on Data
نویسندگان
چکیده
Dual edge triggering is an emerging effective method for reducing the power consumption in the clock distribution network. This paper compares three existing design of dual edge triggered flip-flop EP_CDFF, EP_CPFF and DET-SAFF with the proposed design of the dual edge triggered flip-flop (DET-FF). The design eliminates the redundant transitions of internal nodes when current data is same as the previous one using conditional technique and also to disable the clock when the input invokes no output changes provide a control circuit. The design significantly reduces the power dissipation. Various TSPICE simulation with different input sequences show that reduction in power is 15.25% of those of the prior art. The design has been simulated using Tanner 13.0 EDA tool with 0.35 μm technology at 25°C temperature
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