Reducing Conflict Misses in Caches

Nearly all modern computing systems employ caches to hide the memory latency. Modern processors often employ multiple levels of cache, with one or more levels on the same die as the processor core. As performance demands increase, it becomes increasingly important for an on-die cache structure to perform well. Inefficient use of the available cache space can become increasingly costly in terms of both speed [1] and power usage [4]. Speed and size constraints often make the case for small on-die caches, with little or no associativity. However, small direct-mapped caches may result in a large number of conflict misses. In order to reduce the number of conflicts, we propose a small structure called the Conflict Detection Table (CDT), which stores the instruction and data addresses of load/store instructions. By using this table, it can be found if a memory access is expected to produce a cache hit. From this information, it can be determined if a cache miss is caused by a conflict with another instruction, and appropriate action can be taken. We propose two caches that employ this conflict detection technique. The first cache, called the Bypass in Case of Conflict (BCC) cache, is a direct-mapped cache that bypasses the cache when a conflict is detected. The second cache, called the Sub-block in Case of Conflict (SCC) cache, is a directmapped cache that fetches only part of the referenced cache line, when a conflict is detected. Experiments have shown that, for a number of applications, the BCC and the SCC can produce less traffic than direct-mapped caches. This leads to decreased power consumption without increasing the average memory access time. Keywords— cache; conflict misses; power reduction; embedded systems