CMOS Implementation of Viterbi Decoder

This paper presents implementation of a soft decision Viterbi decoder suitable for convolution codes with short constraint lengths. The decoder is based on a property of Viterbi algorithm that states “if the survivor paths from all possible states at time n are traced back then with high probability all the paths merge at time n-L where L is the survivor path length”. Pipeline structures are introduced in Viterbi decoder, which increases the decoding speed. Because of the pipeline structure there is a little increase in hardware complexity. The implemented Viterbi decoder operates on a block of received data and the block length decides the decoding speed. The decoder is simulated and synthesized on Altera’s Quartus-II targeting on Stratix-EP1S10B672C6 by writing structural VHDL Description. The static CMOS transistor level circuit simulation is done using Berkeley SPICE for 0.35m MOSIS technology. Key-Words: Convolutional encoder, Viterbi decoder, Survivor path length, Euclidean distance, Add Compare Select unit, Branch Metric unit.