Test Pattern Generation Using Boolean Satis ability
نویسنده
چکیده
This article describes the Boolean satis ability method for generating test patterns for single stuck at faults in combinational circuits This new method generates test patterns in two steps First it constructs a formula expressing the Boolean di erence between the unfaulted and faulted circuits Second it applies a Boolean satis ability algorithm to the resulting formula This approach di ers from previous methods now in use which search the circuit structure directly instead of constructing a formula from it The new method is general and e ective it allows for the addition of heuristics used by structural search methods and it has produced excellent results on popular test pattern generation benchmarks
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