Adaptive Router Design for Networks-On-Chip on FPGA using Buffer Resize Technique
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چکیده
Compared to buses Networks-on-chip have a relative area and delay overhead. These can be reduced in application specific systems where heterogeneous communication infrastructure provide high bandwidth in a localized fashion and reduce underutilized resources. For general purpose systems, design time techniques are not efficient. One important technique for improving area and/or performance of NoCs for general purpose systems is to consider dynamic adaptation of the resources at runtime. This paper proposes the adaptive buffer resize technique for NoCs.
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