Improved Version of 128 Bit Binary Adder design using QCA with Area Efficiency and High Speed

Among the emerging technologies recently proposed as alternatives to the classic CMOS, Quantum-dot cellular automata (QCA) is one of the most promising solutions to design area efficient and very high speed digital circuits. As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. According to recent analysis the minimum limit for transistor size may be reached. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit, even though the design of logic modules in QCA is not always straightforward. In this survey a binary adder is taken for analysis and a new adder is designed based upon QCA technology. The aim of this proposed technique is that to reducing number of majority gates used in the design. This will lead to reduce number of QCA cells so that total area of binary adder circuit can be minimized compare to previous designs. The proposed 128 Bit QCA adder is implemented on Xilinx ISE and designed using Verilog HDL.