An efficient and reconfigurable VLSI architecture for different block matching motion estimation algorithms
نویسندگان
چکیده
| This paper describes a VLSI architecture which can be recon gured to support both Full Search Block{Matching algorithm and 3{step Hierarchical Search Block{Matching algorithm. By using a recon gurable register{ mux array and a parameterizable adder tree, the 2{D array architecture provides e cient real time motion estimation for many video applications. We also propose a memory architecture and an associated switching network to solve the simultaneous data access problem.
منابع مشابه
A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation
A new efficient type I architecture for motion estimation in video sequences based on the Full-Search Block-Matching (FSBM) algorithm is proposed in this paper. This architecture presents minimum latency, maximum throughput and full utilization of the hardware resources, combining both pipelining and parallel processing techniques. The implementation of an array processor for motion estimation ...
متن کاملVLSI architectures for block matching algorithms using systolic arrays
|In this paper, we investigate hardware implementation of block matching algorithms (BMAs) for motion estimation of moving sequences. Using systolic arrays, we propose VLSI architectures for the two-stage BMA and full search (FS) BMA. The two-stage BMA using integral projections reduces greatly computational complexity with its performance comparable to that of the FS BMA. The proposed hardware...
متن کاملImproving Energy Efficiency of Block-Matching Motion Estimation Using Dynamic Partial Reconfiguration
In this paper, energy-efficient architecture for Variable Block Size Motion Estimation (VBSME) is proposed to fully utilize dynamic partial reconfiguration capability of programmable hardware fabric in the heterogeneous computing environment. Dynamic Partial Reconfiguration is a unique feature of FPGAs that makes best use of hardware resources and power by allowing adaptive algorithm to be impl...
متن کاملFast VLSI Implementation for Low Power Motion Estimation Removing Redundant Memory Data Access
| This paper presents a new VLSI architecture of the Motion Estimation in MPEG-2. Previously , a number of full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the architectures have an ineeciently large number of external memory access. Recently, to reduce the number of accesses in one candidate block, a block mat...
متن کاملAn Efficient Successive Elimination Algorithm for Block-Matching Motion Estimation
Low power VLSI video compression processors are in high demand for the emerging wireless video applications [1]. Video compression processors include VLSI implementation of a motion estimation algorithm. Many motion estimation algorithms are found in the literature. Some of them are fast but can not guarantee an optimal solution; they can be stuck in a local optima. Such algorithms are fast, co...
متن کامل