Test Scheduling and Control for VLSI Built-In Self-Test

The problem of exploiting parallelism in the testing of VLSI circuits with built-in self-test (BIST) was first introduced in [l]. In this paper, this problem is examined in detail using a broader modeling foundation and new algorithms. A hierarchical model for VLSI circuit testing is introduced. The test resource sharing model from [l] is employed to exploit the potential parallelism. Based on this model, very efficient suboptimum algorithms are proposed for defining test schedules for both the equal length test and unequal length test cases. For the unequal length test case, three different scheduling disciplines are defined and scheduling algorithms are given for two of the three cases. Data on algorithm performance are presented. The issue of the control of the test schedule is also addressed, and a number of structures are proposed for implementation of control.