Comparison of Power Consumption in Array Multiplier with and without SVL Circuit
نویسندگان
چکیده
In this paper, we performed the comparative analysis of power consumption of array multiplier circuit implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 10 transistorStatic Energy Recovery CMOS adder and 8 transistor CMOS (SERF) circuits. At first, the circuit was simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In the multiplier architecture chosen, less power consumption was observed being consumed by the SERF adder based multipliers applied with SVL circuit. .
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