A 0.8- m CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links
نویسندگان
چکیده
A receiver targeting OC-48 (2.488 Gb/s) serial data link has been designed and integrated in a 0.8m CMOS process. An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3 oversampled so that transitions can be detected to determine bit boundaries. The design of a transmitter for the high-speed serial data is also described. The complete transceiver occupies a die area of 3 3 mm2:
منابع مشابه
A 0.8-pm CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links
A receiver targeting OC-48 (2.488 Gbk) serial data link has been designed and integrated in a O.8-pm CMOS process. An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3x oversample...
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