Studies on Multi-Cycle Paths of Sequential Circuits

The timing analysis and optimization of sequential circuits become more and more important with the advances of VLSI technologies. We should cope with the clock frequency more than 2 GHz near the future. The clock frequencies of sequential circuits are decided based on the maximum delay time of paths between clocked flip-flops under the assumption that all paths propagate signals within one clock cycle. The assumption is violated in many circuits including multicycle paths on which signals can be propagated with 2 or more clock cycles. At present, such multi-cycle paths are detected and manipulated by hands, but should be detected and manipulated automatically for the correct timing analysis. In the thesis, we formalize multi-cycle paths and propose two detection methods of multi-cycle paths. We also describe the decision of the clock frequency, timing verification and logic optimization with considering the number of allowable clock cycles for signal propagations. First, we focus on multi-cycle paths between flip-flops which are guarded with wait states, and formalize such multi-cycle paths based on update cycle of flipflops. Second, we propose a detection method of multi-cycle paths based on a symbolic state traversal of FSMs (Finite State Machines) using BDD’s (Binary Decision Diagrams). The method detects multi-cycle paths based on the update cycle analysis of flip-flops. The method computes reachable states from the initial state of FSM using symbolic state traversal of FSM. Then the method computes allowable clock cycles of each path between flip-flops and detects multi-cycle paths. ∗Doctor’s Thesis, Department of Information Systems, Graduate School of Information Science, Nara Institute of Science and Technology, NAIST-IS-DT9861205, February 5, 2001.