Correct Reuse of Complex Design Units During High Level Synthesis: Veri cation Issues
نویسندگان
چکیده
The paper proposes a new model for veriication and high level synthesis (re)using complex units like co-processors. The model is called FSMC (FSM with Co-processors) and is an extension of the FSMD model (FSM with Data path). The veriication method is based on model checking. It permits to analyze the properties and consistency of the whole system and, particularly, the correct (re)use of design blocks.
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