A 2.9mW ADPLL-BASED FREQUENCY SYNTHESIZER FOR HIGH SPEED CLOCK GENERATION
نویسندگان
چکیده
The cores of the ADPLL-based frequency synthesizer are digital controlled oscillator (DCO) and phase frequency detector (PFD). A modified digitally controlled delay element (DCDE) with characteristics of its monotonicity and insensitivity to PVT variations is presented for the DCO design. We also proposed a new PFD architecture that can finish phase and frequency comparison and adjustment in one reference cycle. The proposed ADPLL-based frequency synthesizer has been designed with TSMC 0.13 um technology model. It can operate from 300 MHz to 1 GHz, and achieve frequency acquisition in fifteen reference clock cycles (worst case scenario). The peak-to-peak jitter of the output clock is less than 120 ps. The total power dissipation of the ADPLL-based frequency synthesizer is 2.9 mW at 1 GHz with a 1.2 V power supply. With the specification, it could be used for high speed clock generation in high speed DSPs applications.
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