Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators

Advanced CMOS processes offer very fast switching speed and high transistor density that can be utilized to implement analog signal processing functions in interesting and unconventional ways, for example by leveraging time as a signal domain. In this context, voltage controlled ring oscillators are circuit elements that are not only very attractive due to their highly digital implementation which takes advantage of scaling, but also due to their ability to amplify or integrate conventional voltage signals into the time domain. In this work, we take advantage of voltage controlled oscillators to implement analogand time-to-digital converters with first-order quantization and mismatch noise-shaping. To implement a time-to-digital converter (TDC) with noise-shaping, we present a oscillator that is enabled during the measurement of an input, and then disabled in between measurements. By holding the state of the oscillator in between samples, the quantization error is saved and transferred to the following sample, which can be seen as first-order noise-shaping in the frequency domain. In order to achieve good noiseshaping performance, we also present key details of a multi-path oscillator topology that is able to reduce the effective delay per stage by a factor of 5 and accurately preserve the quantization error from measurement to measurement. An 11-bit, 50Msps prototype time-to-digital converter (TDC) using a multi-path gated ring oscillator with 6ps of delay per stage demonstrates over 20dB of 1st-order noise shaping. At frequencies below 1MHz, the TDC error integrates to 80fsrms for a dynamic range of 95dB with no calibration of differential non-linearity required. The 157x258μm TDC is realized in 0.13μm CMOS and operates from a 1.5V supply. The use of VCO-based quantization within continuous-time (CT) Σ∆ ADC structures is also explored, with a custom prototype in 0.13μm CMOS showing measured performance of 86/72dB SNR/SNDR with 10MHz bandwidth while consuming 40mW from a 1.2V supply and occupying an active area of 640μm X 660μm. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which we show achieves first-order noise-shaping of its quantization noise. The quantizer structure allows the second order CT Σ∆ ADC topology to achieve third order noise 3 shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching (DEM) of the DAC elements. Thesis Supervisor: Michael H. Perrott Title: Associate Professor