Block Based Compression Storage

In this paper we present some preliminary performance evaluations of the Block Based Compression Storage (BBCS) scheme, that consists of a sparse matrix representation format and an associated Vector Processor (VP) architectural extension, designed to alleviate the performance degradation experienced by VPs when operating on sparse matrices. In particular we address the execution of Sparse Matrix Vector Multiplication (SMVM) algorithms. First we introduce a specialized VP functional unit to support the part of the architectural extension that does the SMVM computation, the MIPA instruction. Subsequently, we consider a set of benchmark matrices and report some preliminary performance evaluations by comparing the BBCS scheme with the Jagged Diagonal (JD) scheme. The simulations of the SMVM algorithm core execution indicate the BBCS scheme always performs better than the JD scheme for large VP section sizes and its performance always lies within a range of at most 10% away from the theoretic ideal performance, independently of the type of the processed matrix, whereas the JD performance is heavily dependent on the matrix type. Furthermore we calculated that the required memory bandwidth for the JD scheme is between 2:49 and 3:12 times higher than the one required by the BBCS scheme.