Mapping Applications to a Coarse-Grained Reconfigurable Architecture
نویسنده
چکیده
Today the most commonly used system architectures in data processing can be divided into three categories: general purpose processors, application specific architectures and reconfigurable architectures. General purpose processors are flexible, but inefficient and for some applications do not offer enough performance. Application specific architectures are efficient and give good performance, but are inflexible. Recently reconfigurable systems have drawn increasing attention due to their combination of flexibility and efficiency. Reconfigurable architectures limit their flexibility to a particular algorithm domain. Two types of reconfigurable architectures exist: fine-grained in which the functionality of the hardware is specified at the bit level and coarsegrained in which the functionality of the hardware is specified at the word level. High-level design entry tools are essential for reconfigurable systems, especially coarse-grained reconfigurable architectures. However, the tools for coarse-grained reconfigurable architectures are far from mature. This thesis proposes a method for mapping applications onto a coarsegrained reconfigurable architecture. This is a heuristic method which tackles this complex problem in four phases: translation, clustering, scheduling and allocation. In this thesis, the Montium tile processor, a coarse-grained reconfigurable architecture, is used to demonstrate the proposed mapping method. In the translation phase, an input program written in a high-level language is translated into a control data flow graph; and some transformations and simplifications are done on the control data flow graph. In the clustering phase, the data flow graph is partitioned into clusters and mapped onto an unbounded number of fully connected Arithmetic Logic Units (ALUs). The ALU structure is the main concern of this phase and we do not take the interALU communication into consideration. In the scheduling phase the graph obtained from the clustering phase is scheduled taking the maximum number of ALUs into account. The scheduling algorithm tries to minimize the num-
منابع مشابه
Exploiting the Distributed Foreground Memory in Coarse Grain Reconfigurable Arrays for Reducing the Memory Bottleneck in DSP Applications
This paper presents a methodology for memory-aware mapping on 2-Dimensional coarse-grained reconfigurable architectures that aims in the minimization of the data memory accesses for DSP and multimedia applications. Additionally, the realistic 2-Dimensional coarse-grained reconfigurable architecture template to which the mapping methodology targets, models a large number of existing coarse-grain...
متن کاملLoop Kernel Pipelining Mapping onto Coarse-Grained Reconfigurable Architecture for Data-Intensive Applications
Coarse-grained reconfigurable architectures (CGRA) provide flexible and efficient solution for data-intensive applications. Loop kernels of these applications always consume much execution time of the whole program. However, mapping loop kernels onto CGRA is still hard to meet performance/cost constraints. This paper proposes a novel approach for automatically mapping loop kernels onto CGRA wit...
متن کاملDesign and Evaluation of a Coarse-Grained Reconfigurable Architecture
Coarse-grained reconfigurable architectures have become more attractive with the increasing requirement of more flexibility and higher performance in embedded systems design. In this paper, we suggest a design space exploration flow that enables effective optimization of reconfigurable architectures through SystemC Modeling. In the suggested flow, application-to-architecture mapping process tri...
متن کاملAn Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
Reconfigurable logic devices (RLDs) are classified as the fine-grained or coarse-grained type based on their basic logic cell architecture. In general, each architecture has its own advantage. Therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In the present paper, we propose a variable grain logic cell (VGLC) architectur...
متن کاملPerformance Improvements of DSP Applications on a Generic Reconfigurable Platform
Speedups from mapping four real-life DSP applications on an embedded system-on-chip that couples coarsegrained reconfigurable logic with an instruction-set processor are presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elements. A design flow for improving application’s performance is proposed. Critical software parts, called kernels, are accelerated on the...
متن کامل