Dynamic Reconfigurable NoC (DRNoC) Architecture: Application to Fast NoC Emulation
نویسنده
چکیده
The aim of this Chapter is to present a highly flexible reconfigurable NoC solution for commercial FPGAs on one side, and on the other side, to provide an innovative approach for fast NoC emulation. The reconfigurable on-chip communication solution that is proposed in this chapter is capable of being reconfigured by means of adapting routers, network interfaces and cores themselves. The main distinguishing characteristic of the presented on-chip communication approach is that it permits to distribute the available on-chip communication resources among different communication topologies and thus, independent and application specific communication strategies can coexist and run in parallel. Furthermore, the proposed solution is not limited to NoCs and it permits to build a variety of on-chip communication. The proposed method in this Chapter for fast emulation provides a rapid way of validating different communication alternatives. The emulation method is based on the original idea of hard core re-usability through the exploitation of partial reconfiguration capabilities of some state of the art FPGAs. Both aspects have been tested and validated using a proof of concept approach and are discussed along this Chapter.
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