FPGA Based Efficient WCDMA DUC for Software Radios Rajesh Mehra

Abstract— This paper presents an efficient method to design & implement WCDMA based digital up converter for Software Radios. The Park McClellan algorithm has been proposed for optimal filter length to reduce hardware requirements. A computationally efficient polyphase decomposition structure is also proposed to optimize both speed and area. The embedded multipliers and LUTs of target FPGA are efficiently utilized to enhance the system performance. The proposed DUC has been designed with Matlab, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-II Pro based xc2vp30-7ff896 FPGA device. The developed DUC can operate at a maximum frequency of 136.37 MHz by consuming 0.10313W power at 25° C junction temperature. The proposed design has been implemented on multiplier based target FPGA to provide cost effective solution for SDR based wireless applications.