RISC-y Memories

The DISTO Data Acquisition System at SATURNE

The DISTO collaboration has built a large-acceptance magnetic spectrometer designed to provide broad kinematic coverage of multi-particle final states produced in pp scattering. The spectrometer has been installed in the polarized proton beam of the Saturne accelerator in Saclay to study polarization observables in the ~ pp → pK~ Y (Y = Λ,Σ or Y ) reaction and vector meson production (φ, ω and ...

Parallel Implementation of Neural Associative Memories on Risc Processors

Processor Design for Digital Flight Control Computer

This paper presents the design and FPGA implementation of a 32bit configurable micro controller. The micro controller contains a 32-bit processor based on RISC-V Instruction Set Architecture, Cache memories, interrupt support, multiplexed buses and a Debug Unit. The processor support all integer arithmetic. Cache memories have various sizes upto 16kB. Prioritized stacked interrupt control is pr...

Low Power Code Generation for a RISC Processor by Register Pipelining

This paper presents the implementation of the compiler technique register pipelining with respect to energy optimization and its comparison against performance optimization. Generally, programs optimized for performance are also energy optimized. An exception to this rule is shown where the use of register pipelining improves the energy consumption by 17% while bringing down performance by 8.8%...

Issues of Advanced Architectural Features in the Design of a Timing Tool

This paper describes a timing tool being developed by a real-time research group at Seoul National University. Our focus is on the issues resulting from advanced architectural features such as pipelined execution and cache memories found in many modern RISC-style processors. For each architectural feature we state the issues and explain our approach.