Selective and transparent acceleration of OpenFlow switches

We present the design and implementation of a transparent and selective offload architecture, accelerating a mature software OpenFlow implementation (Open vSwitch) using a programmable network processor. Our design combines the flexibility offered by software OpenFlow implementations with the performance of specialised switch hardware. It is targeted at accelerating the emerging class of edge/gateway switches which are becoming increasingly important in some SDN designs. Our prototype implementation offers at least a 8-10x performance improvement over software only Open vSwitch for benchmarks where the majority of the packets can be handled by the network processor.