Cmos Circuit Veriication with Symbolic Switch-level Timing Simulation

Verifying a Static RAM Design by Logic Simulation

A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits implementing the system speciication will produce a particular response to a sequence of simulation commands. Three-valued modeling, where the third state X indicates a signal with unknown digital value, can greatly reduce the number of patterns that need to be simulated for complete veriicati...

Exploiting symmetry when verifying transistor - levelcircuits by symbolic trajectory

|We describe the use of symmetry for veriication of transistor-level circuits by Symbolic Trajectory Evaluation (STE). We present a new formulation of STE which allows a succint description of symmetry properties in circuits. Symmetries in circuits are classiied as structural symmetries, arising from similarities in circuit structure, data symmetries, arising from similarities in the handling o...

A Mathematically Precise Two-level Formal Hardware Veriication Methodology

Theorem-proving and symbolic trajectory evaluation are both described as methods for the formal veriication of hardware. They are both used to achieve a common goal|correctly designed hardware|and both are intended to be an alternative to conventional methods based on non-exhaustive simulation. However, they have diierent strengths and weaknesses. The main signiicance of this paper is the descr...

Current Waveform Simulation for CMOS VLSI Circuits Considering Event-Overlapping

Accurate current analysis is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, and so on. A charge-based current model for CMOS gates is presented in this paper. The current waveform of a CMOS gate during a transition consists of three components: one occurs when the input changes and the others exist only when the output changes. These three...

CMOS circuit verification with symbolic switch-level timingsimulation