Design Based Yield Improvements (DBYI)

The manufacturability of integrated circuits can be improved at design level by incorporating modifications in the structure of the IP components (cores, cells, memories) and of interconnections, as well as changes in the design methodology and flow. In this tutorial we will describe the types of design improvements that can be introduced in the design of large integrated circuits, and the potential advantages they can have for yield. These include modifications in IP cores, standard cell libraries and memory blocks, as well as interconnections. The potential impact of different techniques on the design flow will also be discussed. We will describe the technology we use to quantitatively estimate and measure yield losses due to random, systematic and parametric effects. This capability is essential to drive design modifications, in order to understand their impact, and the trade-off between conflicting requirements.