Resequencing Cells in an ATM Switch

atm switching systems are required to maintain ordering for cells within a given virtual circuit This is most commonly achieved using a switching system in which cells in a given virtual circuit are routed along a common path through the switch ing system This solution has the drawback that it can lead to signi cant virtual circuit blocking unless the switching network is engineered with a large speed ad vantage relative to the external links Switching systems in which cells are routed independently on the other hand can balance the load dynamically and operate with a minimal speed advantage This report describes a resequencer that can be used with such a switching system to put cells back in the proper order gives an economical implementation of such a resequencer and reports on a simulation study of its e ectiveness Resequencing Cells in an ATM Switch