Synthesis Techniques for Pseudo-Random Built-In Self-Test
نویسنده
چکیده
This technical report contains the text of Nur Touba's thesis "Synthesis Techniques for Pseudo-Random Built-In Self-Test." The thesis appendices have appeared as CRC Technical Reports, and are not included here.
منابع مشابه
Low Power March Memory Test Algorithm for Static Random Access Memories (TECHNICAL NOTE)
Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...
متن کاملSynthesis Techniques for Pseudo-Random Built-In Self-Test Based on the LFSR
The structure of test system based on application built-in self-test (BIST) circuitries has been proposed. The main idea is oriented on minimization of hardware overheads and dealt with automatization of BIST-circuitries generation. Test generator based on linear feedback shift register (LFSR) provides two types of testing pseudorandom and deterministic. The proposed modified Berlekamp–Massey a...
متن کاملBuilt-In Reseeding for Serial Bist
Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost, testing using automatic test equipment (ATE) makes it hard to test the circuit while in the system. In this paper, we present a technique for built-in reseeding. Our technique requires no storage for the seeds. The s...
متن کاملSynthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new technique for synthesizing combinational mapping logic to transform the set of patterns that are generated. The goal is to satisfy test length and fault coverage requirements while minimizing area overhead. For a given...
متن کاملOn Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate efficient patterns to be used during BIST test pattern generation. The main idea is that test patterns detecting random pattern resistant faults are not embedded in a pseudo–random sequence as in existing techniques, but rat...
متن کامل