A Low Power Soft Core for Multi-Standard Video Applications

Product life time and design reusability have become critical objectives for todays system on chip designs. To achieve long life cycles for high performance devices calls for increased flexibility of intellectual property (IP) cores as well as SoC solutions. While programmability is one of the key factors in achieving this goal, its impact on die size and increased power consumption should be kept minimal. Application tailored configurable IP cores with power saving capabilities and level-headed programmability are key elements for building such novel SoC designs. ASIC-like robustness using encapsulated firmware thereby allows for both future proof solutions and a consistent verification and test environment. In this paper, we present an IP core for power-efficient execution of memory intensive applications like H.264 and WMV9 video stream decoders. It is shown how the core concept can be tailored to meet the requirements of different video resolutions. The IP core architecture is based on a novel, low-overhead design template for signal processing accelerators. It allows for being tailored towards a specific application domain while simultaneously providing sufficient programmability. The architecture template is presented in detail in the paper. Based on the SAMIRA DSP, a DSP core tailored for software defined radio applications, which was successfully produced in 0.13um technology, we show how we map a complex application on multiple digital signal processors which were automatically generated using our automatic core generation environment. Furthermore a software design methodology for developing the firmware for such a multiprocessor system is presented. The methodology is using different levels of instruction set granularity to generate an optimized scheduling and intercommunication scheme for the embedded IP core.