Analog Component Control Component Internal Events Internal Control Signals Analog Output Signals Analog System Input

This paper deenes a VHDL-AMS subset for be-havioral synthesis of analog systems. The subset includes language constructs for describing most of the functional aspects pertaining to analog systems. Besides , these constructs can be implemented with electronic circuits. Functional aspects, which can be expressed with the subset, relate to two interacting parts. The analog part continuously processes analog signals, while the control part generates control signals for con-guring the ow of signals in the analog part. However , some language constructs have to be constrained or augmented, so that they become eeective for synthesis. To motivate that constructs in the subset can be synthesized, we present, by means of an example, how VHDL-AMS programs are compiled into an intermediate format. The intermediate format can be either directly mapped to components from a component library , or used for further synthesis-related optimization steps. Finally, we discuss a complete experiment for specifying of functionality, compiling the speciica-tion, and its mapping to electronic components.