An Analytical Approach for Soft Error Rate Estimation of SRAM-Based FPGAs
نویسندگان
چکیده
SRAM-based FPGAs are increasingly becoming more popular in applications where high dependability, low cost, and fast time-tomarket are important constraints. However, these devices are more susceptible to single-event upsets (SEUs) compared ASIC designs. The error models of SRAM-based due to SEUs are more complicated than those of ASICs since soft-errors in the configuration memory result in permanent errors in the user application. In this work, we investigate different error models for SRAM-based FPGAs due to soft errors and present analytical soft error rate estimation for these devices.
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