High Speed and Low Power Multiplier Design Using Mtcmos Technique
نویسندگان
چکیده
MTCMOS is an effective circuit level technique which has multiple threshold voltages in order to optimize delay and power. Low threshold voltage MOSFETs enhance the speed performance, while the high threshold voltages MOSFETs minimize the static leakage power. The above technique is adopted in parallel multiplier with level shifter interface which gives supply voltage for MTCMOS transistors. By implementing 65-nm technology, the parallel multiplier shows on average propagation delay of 2.41ns and average power of 1.82mW. Using Tanner EDA Tool schematic simulation is done by S-edit, propagation delay is calculated by the W-edit and the power is calculated by the T-spice, layouts and 3D model are done by the Micro wind. Keywords— MTCMOS, Level shifter, Parallel Multiplier
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