Design of a DSP for Improving FFT Computing with the Vectorized Mechanisms

In order to improve the performance for real-time application, current digital signal processors use VLIW architectures to increase the degree of instruction level parallelism (ILP). There exist two factors making the ILP barriers; one is the hardware resource limitation for all parallel instructions. Another is the dependence relations between instructions. For coping these hazards, in this paper, we designs a VLIW architecture processing core, called DVBT-DSP, molded by the FFT algorithm and use the software pipelining mechanism to schedule the loop to achieve the highest ILP degree in executing the FFT butterfly algorithms. Furthermore, in order to provide the smooth data stream for pipeline operations, the vectorized modulo addressing mode is designed to collect the regular but discrete data to a continuous vector. The simulation results show that the DVBT_DSP has double performance of the C6200 for the FFT processing.