PROR compaction scheme for larger circuits and longer vectors with deterministic ATPG
نویسندگان
چکیده
Reverse order restoration ROR techniques have found great use in sequential automatic test pattern generation ATPG, esp. spectral and perturbation-based ATPG. This paper deals with improving ROR for that purpose. We introduce parallel-fault multipass 2-level polynomial reverse order restoration PROR algorithms with constant complexity of the form H(n)G(n) + c where H(n) is the number of vectors to be released this iteration and G(n) is the attenuation factor. In PROR H(n) = n and G(n) here is 1−H(n)/no vectors with c about 1 to 64, where n is the number of iterations, the fault has been hanging around in the compactor and k is the polynomial complexity of the algorithm, in each iteration. k is variant and can take on any real value. We also divide the vector length such that it has a maximum of 10000 units at best, so that if the vector length is greater than 10000, it is still rounded to 10000 by considering a bigger chunk size. We also added PODEM of backtrace limit 30 on the last vector to get a faster and better quality test set. On contrast to algorithms which do not have results reported on large circuits and on longer vector lengths, we showcase our algorithm. For example, on b22, we achieved a 94.36% FC in 1.31 days with VL 146476.
منابع مشابه
Implementation of Compaction Algorithm for Atpg Generated Partially Specified Test Data
In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault model is considered. The programs are developed for...
متن کاملCompact Test Generation Using a Frozen Clock Testing Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach to generating compact test sequences for sequential circuits. Our approach combines a conventional ATPG algorithm, a technique based on the frozen clock testing strategy, and a dynamic compaction method based on a genetic algorithm. The frozen clock strategy temporarily suspends...
متن کاملAn Efficient Deterministic Test Pattern Compaction Scheme Using Modified IC Scan Chain
In this paper, we propose a new scheme for Built-In Self-Test (BIST) that uses an LFSR obtained by adding feedback loops to the IC boundary scan chain. This LFSR first generates random patterns to cover easy-to-test faults and after the random testing phase it is partially loaded with seeds to generate deterministic vectors for hard-to-test faults. The seeds are obtained by solving systems of l...
متن کاملcient Spectral Techniques for Sequential ATPG
We present a new test generation procedure for sequen tial circuits using spectral techniques Iterations of lter ing via compaction and spectral analysis of the ltered test set are performed for each primary input extracting in herent spectral information embedded within the test se quence This information when viewed in the frequency domain reveals the characteristics of the input spectrum The...
متن کاملEfficient Sequential ATPG for Functional RTL Circuits
We present an efficient register-transfer level automatic test pattern generation (ATPG) algorithm. First, our ATPG generates a series of sequential justification and propagation paths for each RTL primitive via a deterministic branch-and-bound search process, called a test environment. Then the precomputed test vectors for the RTL primitives are plugged into the generated test environments to ...
متن کامل