Design and Implementation of Turbo Decoder for Advanced T-DMB System

Iterative decoders such as turbo decoders have become integral components of modern broadband communication systems such as Advanced Terrestrial DMB (AT-DMB) system because of their ability to provide substantial coding gains. This paper presents a design and FPGA implementation of turbo decoder for AT-DMB system which enables high quality mobile multimedia broadcasting services that exceeds current DMB service's quality and contents capability. The turbo decoder uses the max-log-map algorithm with simple min function. It features an interleaver address generator that computes the interleaved addresses for four block sizes enabling it to quickly switch context to support different data services. The decoder was implemented on a Xilinx Virtex-4 XC4VLX200 device with other functional blocks.