Flip Chip on Organic Substrates

The attachment of a flip chip of moderate size and pitch to an organic substrate has lost much of its mystique in recent years. A small but increasing number of companies, including several contract manufacturers, is establishing flip chip capabilities. This can, in fact, be done in a step by step fashion and with moderate investments in facilities, equipment and training. Still, since only the few can afford to simply remain conservative in today’s market, implementation of the technology will require an ongoing optimization supported by a sizable R&D organization. Overall cost, yields and reliability are sensitive to a multitude of materials, design and process parameters and their interactions. Assembly yields depend, among other, on design, placement accuracy, substrate pad and solder mask tolerances, ball height statistics, substrate warpage, and fluxing technique. Assembly reliability varies with encapsulant and flux type, chip passivation, solder joint number and distribution, solder mask surface morphology and chemistry, laminate chemistry, substrate rigidity and pad metallurgy, and various process parameters in a rather complex fashion. All of this is exacerbated by a trend towards larger die, finer pitches and smaller standoffs, as well as the continuous development of new, improved and/or alternative materials. Observed dependencies can, however, apparently be rationalized and generalized on the basis of an understanding of the underlying mechanisms. INTRODUCTION The attachment of flip chip to organic substrates, whether as Direct Chip Attach (DCA) or as part of component manufacturing, offers a series of potential advantages ranging from cost to performance and achievable I/O count and distribution. High I/O die may only be accommodated by an area array, the only questions being substrate (ceramic or organic) and interconnect (solder or conductive adhesive). Area arrays may also significantly shorten signal paths, as well as minimizing electromagnetic interference (EMI) which is a concern for RF applications. Furthermore, a reasonably even distribution of power across the die, rather than bussing in from the edge, may be important for high power applications. The minimization (elimination) of package levels may also make the attachment of relatively low-I/O flip chip cost effective. The latter in particular is here driving an increasing number of companies to implement the technology. One attractive feature is that a company may implement flip chip capabilities in a step-by-step fashion as far as investments in facilities, equipment and training are concerned. For example, depending somewhat on the type of existing equipment a regular SMT assembly line might be upgraded to allow prototyping and low volume flip chip production for less than $500,000. Importantly, such an upgrade does not have to slow down or limit the equipment in use for regular SMT. The decision to go with flip chip in a specific application may therefore be made on a case-bycase basis. A contract manufacturer may, for example, establish prototyping and small-volume capabilities, deferring scale-up until a large-volume customer comes around. At the other end of the spectrum, of course, a complete high volume flip chip assembly line may cost $57M and occupy roughly 2,000 ft [1]. The development of a flip chip process for a specific product may, however, require considerable insight and sound judgment. Materials or process changes that were not even recognized as such at the time have later been found to seriously affect product quality. Although we are starting to codify a considerable amount of data and understanding in various ways, the technology is not yet quite mature enough for anyone to write a general process ‘cook book’ without being dangerously naive, instantaneously outdated and/or impractical. So far, there is therefore no substitute for the ongoing support from a large R&D organization. The following offers a brief overview of the technology and some of the issues with emphasis on effects of materials, design and process parameters. This is all based on practical experiences from individual customer applications, results of internal R&D efforts, and basic insights gained through Universal Instruments’ research consortia. Emphasis is placed on flip chip attachment to organic substrates with eutectic SnPb solder joints. References are, however, made to high-Pb, no-Pb and conductive adhesive approaches.