Νmos-based Sorters for Multiplier Implementations

نویسندگان

  • E. Rodríguez-Villegas
  • M. J. Avedillo
  • J. M. Quintana
  • G. Huertas
  • A. Rueda
چکیده

The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing a which uses a sorter as the main building block. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using νMOS circuits which allow to improve previous results for multipliers based on a similar architecture.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Efficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields

This paper presents two efficient implementations of fast and pipelined bit-parallel polynomial basis multipliers over GF (2m) by irreducible pentanomials and trinomials. The architecture of the first multiplier is based on a parallel and independent computation of powers of the polynomial variable. In the second structure only even powers of the polynomial variable are used. The par...

متن کامل

Reducing Hardware Complexity of Wallace Multiplier Using High Order Compressors Based on CNTFET

   Multiplier is one of the important components in many systems such as digital filters, digital processors and data encryption. Improving the speed and area of multipliers have impact on the performance of larger arithmetic circuits that are part of them. Wallace algorithm is one of the most famous architectures that uses a tree of half adders and full adders to increase the speed and red...

متن کامل

Differential Implementations of Threshold Logic Gates

2. CAPACITIVE SOLUTIONS This paper reviews differential implementations of threshold logic gates, detailing two classes of solutions: capacitive (switched capacitor and floating gate), and conductance/current. The concept underlying capacitive TLGs is the use of an array of capacitors to implement the weighted sum of inputs. The idea was introduced as early as 1966 [6]. Capacitive TLGs can be c...

متن کامل

Neuron-MOS Current Mirror Circuit and Its Application to Multi-Valued Logic

A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by VT (threshold voltage), compared with the conventional...

متن کامل

Comparative Study of Approximate Multipliers

Approximate multipliers are widely being advocated for energy-efficient computing in applications that exhibit an inherent tolerance to inaccuracy. However, the inclusion of accuracy as a key design parameter, besides the performance, area and power, makes the identification of the most suitable approximate multiplier quite challenging. In this paper, we identify three major decision making fac...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1999