Analysis of Impact of Transistor Aging Effects on Clock Skew in Nano-scale Cmos

2011 Transistor aging effects in Nano-scale CMOS result in transistor performance degradation over the device lifetime. The primary physical mechanism behind transistor aging is Bias Temperature Instability (BTI). Such transistor aging results in circuit performance degradation over time. In this research we are interested in analyzing the impact of the BTI aging effect on clock skew in on-chip clock distribution networks. Clock skew is an important parameter in the clock distribution. It is defined as the maximum time difference between the clock signals received at different end points of a clock distribution network on a chip. The reason for clock skew could be process variations, temperature, or capacitance differences across the clock network. Ideally the clock signal has to be fully synchronous everywhere on a chip (i.e. clock skew of zero), but in reality we get some limited clock skew in the order of a few Pico-Second. If clock skew becomes too high, it can result in timing errors in synchronous designs. In this research, we have analyzed and quantify the impact of transistor aging effects on clock skew. We have simulated an H-tree clock distribution network and analyzed how the transistor aging affects clock skew over a period of 2 years. Our results show that the V t mismatch and low temperature mismatch induced clock skew reduces as a result of transistor aging over time, whereas capacitance mismatch and high temperature mismatch induced clock skew increases over time a result of transistor aging. In a 32nm technology node, the clock skew aging could be in the range of-26% to +36% depending on mismatch cause of clock skew. I certify that the Abstract is a correct representation of the content of this thesis. _____________________________ ___________ Chair, Thesis Committee Date ACKNOWLEDGEMENTS I would like to thanks my thesis advisor Dr. Hamid Mahmoodi for his invaluable guidance and support towards the completion of my thesis. I would also take this opportunity to thank my committee member Dr. Hao Jiang for his assistance. I am grateful to the School of Engineering and the team of NECRL (Nano Electronics and Computing Research Lab) for providing me with the necessary tools and other resources required to complete this project. I would like thank my family members and friends for their help and cooperation during my work.