High-level condition expression transformations for design exploration

Data intensive applications (i.e., multimedia) are clearly dominated by data transfer and storage issues. However, after removing the data transfer and address related bottlenecks, the control-flow mapping issues remain as important implementation overhead in a custom hardware realisation. The source of this overhead can be due to the presence of complex conditional code execution, loops or the mixed of both. In this work, we focus on optimising the behaviour of the conditional code which is dominated by complex condition test expressions. Our transformations aim in a first stage at increasing the degree of mutually exclusiveness of the initial condition trees. This step is complemented by optimising the decoding of the test expressions. In a second stage, architecture exploration is performed by trading-off at the highlevel gate count against critical-path delay for the resulting code. We demonstrate the proposed transformations on a real-life driver using conventional behavioral synthesis tools as synthesis back-end. The driver selected represents the crucial timing bottleneck in a scalable architecture for MPEG-4 Wavelet Quantisation. Using our approach, we have explored in a very short time the design space at the high level and we have obtained a factor 2 reduction of the critical path with a smaller gate count overhead when compared to traditional RT or high-level synthesis based approaches, even when applied by experienced designers