Power Optimization of 4x4-Bit Pipelined Array Multiplier
نویسندگان
چکیده
In this paper, we presented a feasible method of pipelined 4x4-bit array multiplier and evaluated the results by the flexible estimation methods, gate simulation or register-annotated simulation. The multiplier architecture is for low power and high speed applications. The experimental results indicated that this internal optimization reduced the power consumption of this circuit effectively.
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