Minimizing total wire length during 1-dimensional compaction

Minimizing the total wire length is an important objective in VLSI layout design. In this paper we consider the problem of minimizing the total wire length during I-dimensional (I-D) compaction. Assume we are given a layout. containing nh horizontal wires, nlJ vertical wires, and rectilinear polygonal layout. components c.omposed of 7lr vertical edges. We present an O(n/, ·nlogn) time algorithm for generating, from the constraint graph corresponding to the initial layout, a layout of minimum lotal wire length, 11 ::::: 1I1J + nr . Our algorithm generates, among all the layouts having minimum total wire length, one orminimumlayout width, assuming that compaction is done along the horizontal direction. We also consider a number of other compaction problems in which a relationship between the layout width and the total wire length is specified. For example, we present an O(llh' nlogn) time algorithm to determine a layout minimizing the objective function 0" W + {j. f, where w is the layout width and I is the total wire length, 0', {j > 0; i.e., we consider optimizing a tradeoff function between the layout width a~<!.Jlt~lotal wire length.