Performance Advantages of Merging Instruction - and Data - Level Parallelism

This report presents a new architecture based on addding a vector pipeline to a superscalar microprocessor. The goal of this paper is to show that instruction-level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute regular vectorizable code at a performance level that can not be achieved using only ILP techniques. We present an analysis of the two paradigms at the instruction set architecture (ISA) level that shows that the DLP model has several advantages: executes fewer instructions, fewer overall operations (by factors as large as 1.7), and generally executes fewer memory accesses. We then analyze the ILP model in terms of IPC. Our simulations show that a 4-way machine achieves IPCs in the range 1.03-1.52 and that by scaling to 16-way, only a 26% of the peak IPC is achieved. We have also studied the DLP machine, and results show that although they are less sensitive to memory latency, its use is limited to highly vectorizable code. The combined ILP+DLP model is shown to perform from 1.24 to 2.84 times better than the 4-way ILP machine. Moreover, when we scale up the ILP+DLP machine, the speedup over the 16-way ILP machine increases to as much as 3.45. All this extra performance is shown to be achieved with very modest control hardware, thus ensuring that clock cycle time is not jeopardized in our proposed architecture.