A Serial-Link Transceiver Based on 8-GSamples/s A/D and D/A Converters in 0.25- m CMOS
نویسندگان
چکیده
This paper presents a transceiver that uses a 4-bit flash analog-to-digital converter (ADC) for the receiver and an 8-bit current-steering digital-to-analog converter (DAC) for the transmitter. The 8-GSamples/s converters are 8-way time interleaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the accuracy of the interleaved sampling clocks to within 10 ps, and reduces systematic coupling noise to less than 18 mV on the 800-mV signal swing. 1.1-nH bondwire inductors distribute the parasitic capacitances at the transceiver input and output, reducing attenuation by 10 dB at 4 GHz. Equalization algorithms using the converters compensate for the 1.5-GHz transceiver bandwidth to allow 8-GSamples/s multilevel data transmission.
منابع مشابه
A Serial-Link Transceiver Based on 8-GSa/s A/D and D/A Converters in 0.25-μm CMOS
This paper presents a transceiver that uses a 4-bit flash ADC for the receiver and an 8-bit current-steering DAC for the transmitter. The 8-GSa/s converters are 8-way time interleaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the accuracy of the interleaved sampling clocks to within 10 ps, and reduces systematic coupling noise to less t...
متن کاملA 0.8-pm CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links
A receiver targeting OC-48 (2.488 Gbk) serial data link has been designed and integrated in a O.8-pm CMOS process. An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3x oversample...
متن کاملA 0.5- m CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling
A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5m HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed when transmitted and immediately demultiplexed when received. This parallelism is achieved by using multiple phases tapped from a PLL using the phase spacing to determine the bit time. Using an 8 : 1 multiplexer yields 4 Gb...
متن کاملA 0.8- m CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links
A receiver targeting OC-48 (2.488 Gb/s) serial data link has been designed and integrated in a 0.8m CMOS process. An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3 oversampled ...
متن کاملA Low-Power 8-PAM Serial Transceiver in 0.5- m Digital CMOS
An 8-PAM CMOS transceiver is described in this paper. Pre-emphasis is implemented without an increase in DAC resolution or digital computation. The receiver oversamples with three fully differential 3-bit ADCs. The prototype transmits at up to 1.3 Gb/s and has a measured bit error rate of less than 1 in 10 for an 810-Mb/s pseudorandom bit sequence transmission. The device, packaged in a 68-pin ...
متن کامل