Across-wafer CD Uniformity Enhancement through Control of Multi-zone PEB Profiles

This paper describes a novel approach to improving across-wafer CD uniformity through the litho-etch sequence. Our approach is to compensate for systematic CD perturbations by employing all available control authority though the litho-etch process sequence. In particular, we find that the most effective control input for regulating spatial variations in CD is found in the post exposure bake (PEB) process step. More precisely, we construct offset models that relate the PEB temperature profiles of multi-zone bake plates to their zone offsets using wireless, in-situ temperature sensors from OnWafer Technologies. A second model relating across-wafer CD to PEB bake plate zone offsets is then identified from CD data measured by CD-SEM. The CD-to-offset model and the temperature-to-offset model are used with knowledge of the resist sensitivity to determine optimal bake plate zone offsets which minimize post-etch CD variation. This is done using constrained quadratic optimization techniques. Partial experimental work and simulation results show the promise of our approach. We demonstrate through simulation that across-wafer CD variation can be significantly reduced for 150nm technology node and beyond.