Spur Reduction Techniques in Direct Digital Synthesizers

This paper reviews spur reduction techniques used in direct digital synthesizers (DDSs) or numerically controlled oscillators (NCOs). First, the classification and operation of conventional DDSs are reviewed. Covered are the pulse output DDS, sine output DDS, fractional divider, and phase interpolation DDS. It is shown that DDSs produce spurs as well as the desired output frequency due to the aliasing of harmonic imperfections in the generated waveform. Next, spur reduction techniques which reduce spurs by destroying the coherence of the aliasing process are discussed. Architectures described are the spurless fractional divider, the Wheatley jitter injection DDS, the randomized DAC DDS, and the nonuniform clock DDS. The spur reduction and phase jitter properties of each architecture are also discussed. Introduction/Review of DDSs Direct digital synthesizers (DDSs) or numerically controlled oscillators (NCOs) directly synthesize frequency waveforms from a fixed reference frequency using digital waveform generation techniques. DDSs can be classified as the pulse output DDS, sine output DDS, fractional divider, phase interpolation DDS, and other minor DDS variations [1]. The major classifications are summarized below. For more detailed descriptions, see References 1, 2, 3, 4, 5, and 6. Pulse Output DDS Figure 1 shows a block diagram of the pulse output DDS and outlines its operation. The pulse output DDS merely consists of an N-bit accumulator set up to add a frequency word K every clock cycle tc or Rn+1 = Mod(Rn + K, 2 N) (1) where Rn is the N-bit register value in the accumulator after the nth clock cycle. One can take the frequency output fo from the carry output as a pulse or from the most significant bit (MSB) of the accumulator as a "square" wave. From the figure, one can see that on average fo = Fo fc (2) where Fo the fractional frequency is F K o N = 2 (3) and where the clock frequency fc is 1/tc. The main limitation of the pulse output DDS is the high degree of time or phase jitter it exhibits. One can see from Figure 1, that the time error between the actual zero crossings of the output and that of an ideal frequency source varies approximately uniformly from 0 to tc. This produces a time jitter of σ t c t ≅ 2 3 (4) Let us define a fractional register value r r F n n o + = + 1 (5) which is related to the accumulator register word Rn by Fract r R n n N ( ) = 2 (6) One can see from Figure 1 that, at sample time ntc, rn is equal to the cycle count elapsed in an ideal oscillator with frequency fo. Thus the elapsed phase is φ π = 2 rn (7) and the value of Rn at a carry is proportional to the phase error of the output pulse. (This will be important in other DDS designs.) Finally, from (4) and Figure 1, one can see that the phase jitter of the unfiltered output is given by