An FPGA implementation for neural networks with the FDFM processor core approach

This paper presents an FPGA implementation of a 3-layer perceptron using the FDFM (Few DSP blocks and Few block RAMs) approach implemented in the Xilinx Virtex-6 family FPGA. In the FDFM approach, multiple processor cores with few DSP slices and few block RAMs are used. We have implemented 150 processor cores for perceptrons in a Xilinx Virtex-6 family FPGA XC6VLX240T-FF1156. The implementation results show that the 150 processor cores for 32-32-32 input-hidden-output layer perceptrons can be implemented in the FPGA using 150 DSP48 slices, 185 block RAMs, and 9676 slices. It runs in 242.89MHz clock frequency and a single evaluation of 150 nodes perceptron can be performed 1.65× 107 times per second.