Selecting ATE Frequencies for Power Constrained Test Time Reduction Using Aperiodic Clock
نویسندگان
چکیده
An aperiodic test clock methodology to reduce test time of wafer sort has been recently proposed. In practice, however, an automatic test equipment (ATE) allows only a small number of clock periods and finding those is a mathematically complex problem. This paper proposes an algorithm for optimal selection of any given number of tester clock periods. Keywords-Aperiodic clock, Test time reduction, Automatic Test Equipment, Scan test, Adaptive clocking
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