Compilation Support for Superscalar Processors

This thesis describes work done in two areas of compilation support for superscalar processors; register allocation and instruction scheduling. Chapter 1 describes an approach to register allocation for superscalar processors that supports dynamic and speculative out-of-order execution of instructions and guarantees precise interrupts without expensive hardware for managing register usage and maintaining an in-order processor state. The approach is called extended register allocation, and is based on a graph-coloring paradigm for storage allocation first introduced by Chaitin in [2]. Chapter 2 presents a novel approach to performing aggressive instruction scheduling in the context of the superscalar IBM RS/6000 processor architecture[4, 5]. The approach seeks to enhance the instruction-level parallelism visible to the processor by speculatively moving instructions across conditional branches at compile-time, and taking appropriate measures to preserve correct program semantics. Results are presented which indicate that speedups of up to 6% are achievable on the existing RS/6000 implementation, while performance gains of up to 54% are possible with simple extensions to the current implementation in conjunction with the aggressive instruction scheduler that has been implemented. Chapter 3 explores the interaction of the register allocation and instruction scheduling [35, 42], and makes an attempt at developing a better understanding of the underlying interdependencies between the two techniques. A novel framework for integrating the two techniques, based on the ideas presented and the concept of coagulation [41,40] is also presented.