An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS

This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ∆Σ DAC in 65 nm CMOS for the 60-GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output resulting in a predominantly digital DAC with only fifteen analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ∆Σ DAC achieves a 53 dB SFDR, −49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ∆Σ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter. Keywords−∆Σ DAC, time-interleaving, MASH, 60-GHz radio, high-speed, IEEE 802.11ad, WiGig.