The Separation Technique: A Method for Simulating Transistors to Aid Integrated Circuit Design

A new technique that uses the transistor itself as a computing element has been developed for simulating transistors on the analog computer. The method is called the separation technique since it separates the highand low-frequency behavior of the simulated transistor. The high-frequency behavior of the transistor is time scaled by a factor (typically one million) suitable for computer simulation. The technique affords a dramatic time saving in simulation programming. The analog computer programmer puts together complex circuits using time-scaled transistors in a manner very similar to the designer breadboarding in the experimental laboratory. Parameters of the system are simulated by potentiometer settings to allow for designer interaction with the simulation. A comparison of pulse responses between a simulated nanosecond logic gate and the actual gate shows virtually identical results. Typical solution times are 10 to 20 ms per solution. This provides a favorable factor of approximately 104 when compared with solution times of existing digital programs. The implication of this dramatic speed-up is the ability to do sensitivity studies and apply optimization procedures to the design of integrated circuits.