Electrical properties of crystalline YSZ films on silicon as alternative gate dielectrics

Crystalline yttria-stabilized zirconia oxide (YSZ) film was successfully deposited on a silicon wafer without an interfacial amorphous SiO2 layer. The film with equivalent oxide thickness teox down to 1.77 nm shows negligible hysteresis and low interface state density, less than 3 × 1011 cm−2 eV−1. The leakage current density for teox = 1.77 nm film, 1.5 × 10−5 A cm−2 at 1 V bias voltage, is five orders of magnitude lower than that for SiO2 with the same equivalent oxide thickness. The results demonstrate that an ultra-thin YSZ film has sufficient resistivity against the formation of an underlying amorphous layer, and can be a promising gate dielectric replacing SiO2 to reduce the feature size of devices. Silicon dioxide (SiO2) has been used as the primary gate dielectric material in field-effect devices since the advent of the first integrated circuit. However, as device scaling continues, one of the more fundamental limits to the scaling of the gate dielectrics is the exponential increase in tunnelling current with decreasing film thickness. For films below 20 Å, the leakage current rises to 1–10 A cm−2 [1], which requires significant power dissipation and will alter the device performance. To reduce the leakage current while maintaining the same gate capacitance, a thicker film with a higher dielectric constant is required. Many materials have been suggested that could replace SiO2 as possible gate dielectrics, such as Ta2O5 [2–4], TiO2 [5], Y2O3 [6], ZrO2 [7–9], ZrSixOx [10] and SrTiO3 [11, 12]. Unfortunately, most of these materials are not thermally stable on silicon. The formation of SiO2 or metal silicides often occurs when these materials are deposited on silicon or during subsequent annealing. Since SiO2 has a lower dielectric constant, an underlying SiO2 layer can reduce the effective capacitance of the film. In addition, the amorphous SiO2 on silicon leaves dangling bonds that may result in electronic defect, disrupting translational symmetry at the interface [11]. McKee et al [11] used one monolayer of strontium silicide to stabilize the interface with silicon, and obtained crystalline oxide on silicon in SrTiO3/BST/ASi/Si systems. However, whether this MBE-based approach can be scaled up to a cost-effective production is a major concern since the deposition of multilayer would make the production process more complicated. Therefore, a simple approach to grow a single-crystalline high-κ layer on silicon is required for the feature-size reduction of the device. Yittria-stabilized zirconia oxide (YSZ, dielectric constant 25–29.7 [9, 13]) is a very good potential gate dielectric because it is predicated to be one of the few materials that can be thermodynamically stable in contact with silicon at 1000 K [14]. Moreover, through the investigation of Schottky barrier heights and band offsets of various metal oxides by the theory of band lineups of semiconductors, Robertson [15] concluded that ZrO2 and ZrSiO4 have a sufficiently large electron barrier for use as an alternative gate oxide. In our previous paper, we found that the amorphous interfacial oxide can be eliminated by the metal Zr (or Y) ions reacting with native silicon oxide on the surface of the silicon substrate, 0268-1242/01/030013+04$30.00 © 2001 IOP Publishing Ltd Printed in the UK L13 Letter to the Editor and commensurate crystalline oxide can be obtained by an appropriate deposition process [16]. In this letter, we will report the electrical properties of ultra-thin crystalline YSZ films on silicon. The films show very low leakage current and high thermal stability on silicon. The YSZ thin films were grown with the pulsed-laser deposition (PLD) technique. Details of our system and the preparation process have been reported elsewhere [16, 17]. Native p-type silicon wafer with a resistivity of 20 cm was used as substrates. The native silicon oxide was removed in situ by metal ions in lower partial pressure and high temperature. The YSZ films were annealed in oxygen gas at 700 ◦C for 10 s. X-ray diffraction patterns of the films showed that the deposited films had a single-crystal orientation. Atomic force microscopy (AFM) investigation showed that the root mean square roughness of deposited films is only about 0.3–0.5 nm, indicating atomically smooth films. Aluminum dots 1 mm in diameter were evaporated on the film surface as an electrode. The capacitance–voltage (C–V ) and current–voltage (I–V ) measurements were made using an HP4155B and a 4192A parameter analyser respectively. The measurement of highfrequency C–V was conducted at 100 kHz. The equivalent oxide thickness teox of YSZ films was calculated from the accumulation capacitance of the high-frequency C–V curve without considering quantum mechanical effects, where teox is the electrical thickness equivalent for SiO2. The interface was investigated by using high-resolution transmission electron microscopy (HRTEM) in a Philips CM 300 operating at 300 kV accelerating voltage, which has a point-to-point spatial resolution of 1.7 Å. Figure 1 shows a cross-sectional HRTEM image of a 9.0 nm YSZ film deposited on an Si(100) substrate after a 700 ◦C, 10 s rapid thermal annealing in reduced oxygen gas. The YSZ films were found to grow epitaxially on Si(100) substrates with crystal orientation correlation YSZ(001) ‖ Si(001) and YSZ[100] ‖ Si[100]. The most obvious point is that there is no amorphous interfacial oxide observed at the interface. The YSZ–Si interface is atomically sharp within the region of the image, but some misfit dislocations can be observed at the interface, which is caused by the mismatch of the lattice constant between the YSZ and the silicon substrate. In general, the thickness of the native amorphous silicon oxide layer on the surface of the Si wafer is about 1.0–2.0 nm. However, no amorphous silicon oxide layer was observed at the YSZ/Si interface in the cross-sectional TEM image; this implies that the native oxide layer had been successfully removed by the bombardment of Zr ions. Moreover, the subsequent deposited YSZ film has sufficient resistivity against oxygen diffusion from the film surface to the interface during deposition and the rapid thermal annealing, which prevent the formation of amorphous silicon oxide at the interface. The detailed explanation for the elimination mechanism of amorphous silicon oxide was reported in our previous paper [16]. Figure 2 shows the high-frequency C–V curves of YSZ films with physical thicknesses 9.0, 12.0 and 21.0 nm, respectively, which were defined by the deposition time based on the 9.0 nm YSZ sample. The measured capacitance density in accumulation is 1.92, 1.53 and 0.94 μF cm−2, which correspond to equivalent oxide thickness teox = 1.77, 2.23 Figure 1. HRTEM image of a 9.0 nm YSZ film on silicon; the dashed line is at the interface. The crystalline interface without an underlying amorphous SiO2 layer can be observed at the atomically sharp interface. and 3.6 nm, respectively. The dielectric constant of YSZ films is slightly thickness dependent: the dielectric constants are ε ≈ 19.8, 20.9 and 22.7 for 9.0, 12.0 and 21.0 nm YSZ samples, respectively. The C–V curve of the film with teox = 1.77 nm shows negligible hysteresis, indicating few unstable trapped charges in the dielectric film, but for a thicker film with teox = 3.60 nm a large hysteresis near 50 mV can be observed from figure 2. This thickness dependence of hysteresis has been observed by other groups, and was attributed to the introduction of mobile ions during deposition [9]. The flatband voltage of YSZ films from the C–V curves is in the range 0.86–0.88 V, the corresponding trapped fixed charges are positive and in the range 4.5 × 1011–7.3 × 1011 states cm−2. Figure 3 is the normalized high-frequency capacitance of a YSZ film with equivalent oxide thickness teox = 1.77 nm. The simulated low-frequencyC–V curve is in good agreement with the experimental data in the accumulation region, indicating smaller hysteresis and low interface state density. According to the Terman method [18], the interface state density can be extracted by comparing the ideal high-frequency C–V curve with the experimental curve, which gives a value of less than 3 × 1011 cm−2 eV−1. Figure 4 shows the I–V curves of a set of films with different thickness. The leakage current density of films is very low compared with that for SiO2 with the same equivalent oxide thickness. At 1 V bias voltage, the leakage current density ranges from 10−6 to 10−5 A cm−2. Compared with SiO2 gate oxide with the same equivalent oxide thickness of 1.77 nm, which has a leakage current density of 1 A cm−2 [1], the YSZ film had five orders of magnitude lower leakage current density than SiO2. This lower leakage current is attributed to the following factors. The first is the increased physical thickness of higher dielectric constant film. The gate leakage current, at least for direct quantum mechanical tunnelling, is exponentially dependent upon the dielectric thickness. The second is the large energy bandgap and Schottky barrier heights (∼1.4 eV) of the YSZ film. Because