Reduction of Substrate Noise in Mixed-Signal Circuits

Digital switching noise is of major concern in mixed-signal circuits due to thecoupling of the noise via a shared substrate to the analog circuits. A signifi-cant noise source in this context is the digital clock network that generally hasa high switching activity. There is a large capacitive coupling between theclock network and the substrate. Switching of the clock produces currentpeaks causing simultaneous switching noise (SSN). Sharp clock edges yieldsa high frequency content of the clock signal and a large SSN. High frequencynoise is less attenuated through the substrate than low frequencies due to theparasitic inductance of the interconnect from on-chip to off-chip. In thiswork, we present a strategy that targets the problems with clock noise. Theapproach is to generate a clock with smooth edges, i.e. reducing both the highfrequency components of the clock signal and the current peaks produced inthe power supply. We use a special digital D flip-flop circuit that operateswell with the clock. A test chip has been designed where we can control therise and fall time of the clock edges in a digital FIR filter, and measure theperformance of a fifth-order analog active-RC filter.